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Dell PowerEdge R630 Owner's Manual

Chipset

The Intel C610 chipset is implemented on the PowerEdge R730 and R730xd.

The QuickPath Architecture consists of serial point-to-point interconnects for the processors. The PowerEdge R730 and R730xd have a total of two QuickPath Interconnect (QPI) links connecting the processors.

  • Each link consists of 20 lanes (full-width) in each direction with a link speed of 9.6 GT/s.
  • An additional lane is reserved for a forwarded clock. Data is sent over the QPI links as packets.
  • The QuickPath Architecture implemented in E5-2600 v3 features four layers.
  • The Physical layer consists of the actual connection between components. It supports Polarity Inversion and Lane Reversal for optimizing component placement and routing.
  • The Link layer is responsible for flow control and the reliable transmission of data. The Link layer also provides independent flow control for each message class going to and from the Routing Layer.
  • The Routing layer is implemented in a distributed manner between all agents that send Intel QPI messages on the ring (Intel QPI Module, Cbo, IIO, HA). The Intel QPI Module provides a routing function for determining the correct ring stop to forward an inbound packet.
  • The Protocol layer is responsible for high-level protocol communications, including the implementation of a MESIF (Modify, Exclusive, Shared, Invalid, and Forward) cache coherence protocol.

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