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157777
January 26th, 2012 08:00
Have the C state issues with R610 and R710 been fixed?
Hello,
A while back when we purchased some PE R710s we had issues with memory errors which were caused by C states being enabled in the BIOS. Dell support recommended that we disabled all C States and that has resolved the issue. This was back in the 2.x BIOS version. Have these issues been resolved in the latest 6.1.0 versions?
Thanks
Nick
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Daniel My
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January 26th, 2012 10:00
Hello Nick
Unfortunately no, once Intel provides the microcode update to resolve this issue we will put it out with our next BIOS release. We may even release an unscheduled update to implement the new microcode once we receive it.
Currently we have no ETA on when this will be released. I apologize for the inconvenience.
The latest BIOS release implemented microcode changes that correct some turbo mode issues with the CPU, but our hardware escalations group informed me that this does not correct the C state voltage issue that causes memory errors.
Thanks
JOHNADCO
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January 27th, 2012 14:00
Gracias!! Daniel
JOHNADCO
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January 26th, 2012 14:00
Where are the C states located in the bios to disable them? We are putting some Datacore servers in and a requirement is disabling them in bios on the hardware hosts.
Daniel My
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January 26th, 2012 16:00
John
The C state options are under the processor settings in the BIOS. The processor settings option should be on the main screen of the system BIOS. In that menu will be an option to enable or disable C states. Some servers also have the option for CE1. You will want to disable that as well. CE1 is the option for speedstep on the CPU that allows it to dynamically change speeds based on demand. When the CPU uses either of these features it changes the voltage on the fly. Since the memory controller is built into the CPU it is also changing the voltage going to memory. The slight microsecond delay in the CPU switching the voltage and letting the rest of the system know that the voltage has changed is what causes the errors.
Thanks
SDM-Hollie S.
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May 8th, 2012 08:00
Hi,
Is there any ETA for this microcode from Intel?
Thanks, Hollie
Daniel My
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May 8th, 2012 10:00
Hello Hollie
I checked with the hardware escalations group again regarding this issue. I was provided with a new answer this time. I was advised that the 6.1 BIOS update released in November corrected the state transition issue. If you are encountering memory errors and have updated to the 6.1 BIOS then you should contact support to troubleshoot the issue.
Because this information conflicts with the original information I was provided by our escalation group I had a meeting with several members of that group. Everyone agreed that the 6.1 update resolved the microcode issue.
Thanks
npolite2
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September 13th, 2012 10:00
It appears that the issue may be be resolved with the 6.3.0 BIOS
* Updated Memory Reference Code to version 2.40. This BIOS update corrects the following issues: * Multi-Bit Errors and Machine Check Errors resulting from Intel erratum BD123 on systems running Intel Xeon Processor 5600 series with C-states enabled. * Intermittent system hangs at POST during memory initialization with three DIMMs Per Channel memory configurations.
MarcinT
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September 20th, 2012 01:00
Anyone knows where can i find information about errata "BD123" ?
I found this pdf from may 2012: ("Intel® Xeon® Processor 5600 Series Specification Update")
but the latest errara is BD121. Reference Number: 323372-017US
Marcin.
changming
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March 5th, 2015 23:00
You need a newer version of that pdf.